5. Parallel I/O Buses
The bottleneck now
shifted to I/O access and I/O bus speed. Multiple I/O devices in a
server were located on one bus and were limited to one bus speed.
This limitation was solved by adding dual-peer and triple-peer I/O buses. This design was possible by adding more I/O controllers called bridges, as shown in Figure 5.
With this design,
peripherals on any bus have independent access to the processors and
memory. This design also allows I/O buses to operate at different
speeds, separating the slow I/O from faster I/O. Buffers in the bridges
allow I/O transfers to queue, reducing latency.
The key benefits of this design included the following:
Twice the I/O bandwidth of single-bus systems—267MB/s (533MB/s) compared to 133MB/s (267MB/s)
Support for more PCI devices than single-bus systems
Balance
of I/O workload and performance by placing high-usage peripherals (such
as the graphics controller and disk controller) on separate buses
6. Highly Parallel System Architecture
Peer I/O buses moved the
bottleneck from the I/O subsystem back to the memory controller. Dual
memory controllers were the next step in chipset evolution. This system
architecture design was called the Highly Parallel System Architecture (HPSA), and is shown in Figure 6.
This architecture also
featured dual peer PCI buses. HP co-developed this powerful technology
with ServerWorks and was the first to bring it to market.
HPSA servers
employing dual memory controllers processed memory requests in parallel,
enabling memory bandwidth to achieve up to 1.6GB/s with 100MHz
(2.12GB/s with 133MHz) SDRAM.
HPSA components include the following:
Assisted Gunning Transceiver Logic plus (AGTL+) bus
Intel Pentium II and III processors
Dual Wide-Ultra SCSI controllers
Dual-peer PCI buses
Dual memory controllers
Interleaved memory
7. Crossbar Switch
The next step in chipset
evolution was to reduce the bottleneck at the memory I/O controllers by
replacing the controllers with a crossbar switch, as illustrated in Figure 7.
The crossbar switch has five ports: two to the memory subsystem, two to the processor subsystem, and one to the I/O subsystem.
Employing
mainframe techniques, the crossbar switch enables each of the five main
ports to transfer data at high speed to each of the other ports,
allowing concurrent read/writes between processors, memory, and I/O.
Although there are two physical system buses, the buses present one
system image logically to the operating system.
